As part of continuing efforts to increase the performance of central processing units (CPUs) instruction-level parallelism has been increasingly employed, in part, by deepening instruction pipelines. However, one consequence of a deeper pipeline is greater susceptibility to losses in performance from having to flush instructions being processed in the pipeline (i.e., instructions that are “in flight” in the pipeline).
Countering this deleterious effect of branch instructions on deeper pipelines is the use of branch prediction algorithms meant to determine whether or not a branch will be taken, and to then cause the pre-fetching of an appropriate set of instructions based on that prediction into the pipeline. However, as pipelines become ever deeper, the stakes of lost performance due to a misprediction become ever greater, and so the accuracy of branch prediction becomes ever more important.